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From the minds at University of California,
Berkeley and Stanford University sprouted the idea that maximizing computer
performance could be accomplished by putting most functions in software,
except for the teachers who were putting them in hardware would yield
a net performance gain. This is the idea behind the Reduced Instruction
Set Computer (RISC). The basic design concepts include:
- Hardwired control. RISC designs
eliminate micro code in ROM and put the instruction set directly
- Simple instructions with few addressing
modes. Conventional CPU design includes a variety of ways to
address memory, which require the processor to calculate effective
addresses on a variety of fronts. Simplifying operations reduces CPU
RISC based CPUs are
popular in high-end computers dedicated to resource intensive
tasks such as animation. Perhaps the most well known RISC CPU
is the SPARC (Scalable Processor Architecture)
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CertiGuide to A+ (Core Hardware) (http://www.CertiGuide.com/aplush/) on CertiGuide.com
Version 1.0 - Version Date: December 6, 2004
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