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Table Of Contents  CertiGuide to A+ (Core Hardware)
 9  Chapter 0001:  Power Supplies - System Board
      9  XV  Demanding Attention Digitally

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XV  Demanding Attention Digitally
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IRQ
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Interrupting

So plan B is to let devices tell the CPU when they need attention. While this might seem inefficient, it is more practical than polling. Imagine you don't have a doorbell. If the doorbell didn't interrupt you, you would have to go check the door every minute or so to see if anybody was there.

Interruptions are handled by Interrupt Controllers. As it was revealed previously, the system board shrank in size by combining parts into ASICs called chipsets. The interrupt controller was one of those devices absorbed into the chipset.

The original IBM PC and XT were designed with a grand total of eight interrupt channels.

The interrupt count started with zero, leading up to seven. When the IBM AT was released with the 80286 CPU, the expansion bus jumped to 16-bits. At the same time, a second interrupt controller was added.

Rather than trash compatibility with the PC and XT, the designers created a cascade so both interrupt controllers could talk to the CPU on the single control line.

The cascade point the designers selected was interrupt number 2 and sent it over to the second interrupt controller. They choose to land at interrupt number 9. If on the rare chance you have an expansion device that needs interrupt number two, it will be pushed over to number nine. Note that interrupt number 9 is usable, if you have any devices that need interrupt number two, the 'faking out' process consumes interrupt number nine.

Interrupt Channels

A few of the interrupt channels are reserved right out of the gate for the PC control and cannot be borrowed. They are 0, 1, 2, 8, and 13.



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