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Ultra3 SCSI103 is the next step in SCSI evolution. Ultra3 SCSI
has a maximum transfer rate of 160 MB/sec using the same 40 MHz bus
speed. The higher transfer rate is possible because the Ultra3 SCSI
protocol is capable of trans-ferring data on both the rising and falling
edges of the clock signals, for a maximum transfer rate of 160 MB/ sec
with a wide 16-bit device.
Ultra3 SCSI includes all the features
of Ultra2 SCSI, including multimode support. In addition, Ultra3 SCSI
adds five features that differentiate it from Ultra2 SCSI:
- Double Transition Clocking: Data can be
transferred twice per clock pulse on the asserting and negating edges
of the clock pulse. This results in two bits of data being transmitted
for each clock cycle. The maximum data transfer rate reaches 160 MB/sec
without increasing the clock rate of the bus, which remains at the Ultra2
speed of 40 MHz.
- Cyclic Redundancy Check (CRC):104 Previous SCSI implementations used par-ity checking
to detect data errors. CRC can detect single-bit and double-bit errors,
all odd number errors, and errors in burst transmissions up to 32 bits
long. This is a huge improvement in error detection that helps maintain
per-formance with marginal cabling or external device hardware and ensures
data protection during hot plug operations.
- Domain Validation:105 This feature checks the integrity of the entire
SCSI bus, including cables, backplanes, and terminations, to ensure
that data transfers can occur at the maximum possible rate. If a problem
is encoun-tered, the data rate is reduced to a speed that the bus can
- Packetized SCSI:106 Packetized SCSI improves data transfer rates in
two ways: A packetized SCSI bus can send multiple commands simultaneously
in packets. It also allows the ability to transfer commands at the
maximum negotiated bus speed. This means that the SCSI commands can
be sent at the 40 MHz bus speed. On a non-packetized SCSI bus, the
SCSI commands are sent individually at 3 MHz.
- Quick Arbitration and Selection:107 Quick arbitration reduces the bus idle time by
allowing devices to arbitrate for the bus as required. With Quick Ar-bitration,
the device informs the controller when it is ready to transfer data
rather than waiting to be polled. Arbitration includes a fairness algorithm
that prevents older devices from being excluded.
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CertiGuide to A+ (A+ 4 Real) (http://www.CertiGuide.com/apfr/) on CertiGuide.com
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